Brake control system defined by field programmable gate arrey

ABSTRACT

A brake control system for a wheeled vehicle includes a field programmable gate array configured to perform the algorithm of brake control subsystems in a typical brake control system for a wheeled vehicle. The brake control subsystems typically include anti-skid control, brake temperature monitoring, built-in tests, and, in the case of an aircraft, nose wheel steering. The system also includes wheel speed sensors, brake temperature monitors, brake valves and associated control circuits, and brake valve monitors respecting brake valve current and voltage. The use of field programmable gate arrays to configure a brake control system avoids the obsolescence and shortened life of control systems previously dependent upon microprocessors and the like.

This application claims the benefit of Provisional Application No.60/359,867, filed Feb. 25, 2002.

TECHNICAL FIELD

The invention herein resides in the art of electronic control systemsand, more particularly, to control systems for aircraft brakes.Specifically, the invention relates to a brake control system defined byfield programable gate arrays and application specific integratedcircuits such as to provide a hardware implementation of a softwarebased brake control/anti-skid algorithm, including brake-by-wire,automatic braking, and brake temperature monitoring. The invention isgenerally applicable to a broad range of control systems, of whichaircraft brakes are simply an example.

BACKGROUND ART

The invention presented in detail herein is set forth with respect to anaircraft braking system and, more specifically, to the anti-skid controlportion of such a braking system. The invention, however, contemplatesadaptation to a broad range of controls in which field programmable gatearrays may be employed for purposes which will become apparent herein.

In the prior art of control systems, and particularly those for aircraftbrakes, the control system was devised of circuitry comprising discretecomponents. Over a course of time, such aircraft brake control systemsevolved to the implementation of dedicated microprocessors or electronicchips, such that the control system design was primarily softwarecontrolled and algorithm dependent. The market for electronic chips hasbeen substantially consumer driven, with little thought to after-marketsupport. Accordingly, the expected life for many electronic systems ison the order of five years. New high density, high speed components areexpected to have operational lives on the order of about seven years.While this is happening “MIL-spec” parts are being removed fromproduction. But, airframe manufacturers expect the avionics of theaircraft to last and be supported for the life of the aircraft—often onthe order of thirty years or more.

Current market trends exacerbate the problem of obsolete parts. Theavionics industry, and others as well, are thus driven to change the waythey do business. While consideration may be given to life-time buys(purchasing and maintaining an adequate quantity of electronics parts toservice the aircraft from the beginning), such an approach is bothexpensive and risky. Similarly, periodic redesigns to obtain the samefunctionality are costly and time consuming. A better approach is toembrace a new technology that is flexible and has a long period ofprojected availability.

Field Programmable Gate Arrays (FPGA), though not previously applied tocontrol systems in general or braking systems in particular, have beenfound to be attractive to fit the avionics needs of the aircraftindustry. It is presently anticipated that FPGA's are projected to beavailable for a long period of time. They are cost effective, they areboth scalable and flexible in application, they involve a low tomoderate risk factor, and they serve to reduce dependency onmicroprocessors that are given to obsolescence.

DISCLOSURE OF INVENTION

In light of the foregoing, it is a first aspect of the invention toprovide a control system defined primarily by field programmable gatearrays in order to avoid the obsolescence and shortened life of suchcontrol systems previously dependent upon microprocessors and the like.

Another aspect of the invention is the provision of a brake controlsystem defined by FPGA's, including all portions thereof previouslydependent upon software or algorithm configurations.

Still a further aspect of the invention is the provision of a brakecontrol system defined by FPGA's, in which all subsystems of the brakecontrol system, such as anti-skid, nosewheel steering, brake temperaturemonitoring, built-in tests, and the like are all implemented throughFPGA's or application specific integrated circuits (ASIC).

The foregoing and other aspects of the invention which will becomeapparent as the detailed description proceeds are achieved by a brakecontrol system for an aircraft in which the various subsystems andcomponents thereof, such as filters, integrators, amplifiers and thelike are all replicated by FPGA's which thereby provide a hardwareimplementation of what was previously configured in software in priorsystems.

Other aspects of the invention are attained by a brake system for awheeled vehicle comprising: a field programmable gate array configuredto perform an algorithm of brake control subsystems taken from the groupcomprising anti-skid control, nosewheel steering, brake temperaturemonitoring, and built-in tests; a wheel speed interface interposedbetween wheel speed transducers of said wheeled vehicle and said fieldprogrammable gate array for presenting signals to said fieldprogrammable array corresponding to instantaneous wheel speed; and abrake temperature interface interposed between brakes of said vehicleand said field programmable gate array and providing signalscorresponding to brake temperature.

DESCRIPTION OF THE DRAWINGS

For a complete understanding of the objects, techniques and structure ofthe invention reference should be made to the following detaileddescription and accompanying drawings wherein:

FIG. 1 is a block diagram of a brake control system made in accordancewith the invention;

FIG. 2 is a circuit schematic of the anti-skid simulation of the controlsystem of FIG. 1;

FIG. 3 is a schematic diagram of the FPGA design of a low pass filteremployed in the subsystem of FIG. 2; and

FIG. 4 is a schematic diagram of the FPGA implementation of a secondorder low pass filter employed in the embodiment of FIG. 2.

BEST MODE FOR CARRYING OUT THE INVENTION

Referring now to the drawings and more particularly to FIG. 1, it can beseen that a brake control system made in accordance with the inventionis designated generally by the numeral 10. Again, while the concept ofthe invention is described in the context of an aircraft brake controlsystem, it will be appreciated that the general concept is applicable toa broad range of control structures.

At the heart of the brake control system 10 is a field programmable gatearray (FPGA) 12, which is of sufficient size to accommodate thefunctions to be performed by the brake control system 10. A wheel speedinterface 14 is interconnected between wheel speed transducers and theFPGA 12 to provide wheel speed signals of a frequency corresponding toinstantaneous wheel speeds in a manner well known and understood bythose skilled in the art. Similarly, a brake temperature interface 16may be interconnected to an appropriate temperature sensor such asthermocouple, thermistor or the like, to receive signals correspondingto brake temperature. The output of the brake temperature interface 16is provided to an appropriate analog comparator 18 which serves as abrake temperature monitoring system, providing outputs to the FPGA 12,as shown.

A second analog comparator 20 is interconnected with anti-skid brakevalves to monitor the valve voltage and valve current and to providecorresponding outputs relevant thereto to the FPGA 12, as shown. A thirdanalog comparator 22 is shown for such other monitoring functions asmight be desired. Those skilled in the art will appreciate that themonitoring of valve voltages and currents, as well as brake temperatureis a common and necessary undertaking in most brake control systems, thecomparator 22 being provided for such additional monitoring as may bedesired.

A buffer 24 is provided to receive external signals such as a weight onwheels signal or the like to provide such inputs to the FPGA 12 asdesired.

A clock 26 and watchdog timer 28 are provided in association with theFPGA 12 for purposes of synchronous operation and timing. A programmemory input 30 is interconnected to a program serial port forprogramming of the FPGA 12 to operate in accordance with a desiredalgorithm. The programming of FPGA's is well known and understood bythose skilled in the art and, once the appropriate transfer functionsare established, may be readily implemented.

An array of discrete output buffers 32 is provided for monitoringcontrol matters such as wheel speed as determined from transducerinterface 14, or further monitoring wheel spin-up signals and the likefrom external sources. The valve control signals are pulse widthmodulation outputs of the FPGA 12 and are provided through filters 34,36and appropriate valve drivers 38, 40 to the anti-skid valves in theembodiment shown. The outputs of the valve drivers are introduced as thevalve voltage and current signals applied to the analog comparator 20.Similarly, the pulse width modulated output from the FPGA 12 is passedthrough the filter 42 and to the various analog comparators 18, 20, 22to establish the referenced analog ramp signal to be employed by suchcomparators in their operative modes.

Filters 44, 46 receive outputs from the FPGA 12 corresponding to thewheel speed signals of associated wheels and pass those signals toperipheral equipment as desired. Similarly, outputs from serial ports ofthe FPGA 12 are passed to appropriate peripheral equipment such asbuilt-in test equipment and the like.

Fundamentally, it should be appreciated that FIG. 1 provides the overallstructure of a brake control system, with the FPGA 12 serving to performthe algorithm of the various subsystems thereof. One such subsystem isthe anti-skid system, shown in FPGA simulation in FIG. 2 and designatedgenerally by the numeral 50. As shown, the wheel speed signal pulsesfrom the interface 14 are applied to a frequency to digital converter 52and then passed through a low pass filter 54 to rid the signal of noise.A second notch filter 56 further refines the signal by eliminating orrejecting signal frequencies attributed to the natural strut frequencyof the associated wheel. A threshold comparator or drop-out circuit 58receives the filtered wheel speed signal and blocks any such signalsindicative of wheel speed below a certain threshold. As is well known tothose skilled in the art, it is generally desired that anti-skidoperation be precluded below a particular velocity threshold such as,for example, 16.9 feet per second.

When operating above the drop out threshold, the filtered wheel speedsignal passes from the circuit 58 to a high pass filter 60 that operatesas a differentiator to generate a signal corresponding to wheeldeceleration. That signal is then passed to a second high pass filter 62which, operating as a differentiator, generates the second derivative ofwheel speed, the same being a signal corresponding to the rate of changeof deceleration. Those skilled in the art will appreciate that theoutput of the second high pass filter 62, corresponding to the rate ofchange of deceleration, is employed to anticipate skids by theassociated wheel. A limiter circuit 64 responds to the output of thehigh pass filter 62 and limits the output thereof such that theanti-skid system responds only to the initiation of the secondderivative output from the circuit 62, such that the second derivativeis an initiating, but not a driving force in the anti-skid operation.

The output of the limiter 64 is passed, along with the output of themodulator 72 to a summing circuit 66, the output of which is theinstantaneous average of the wheel speed signal. The output of thesumming circuit 66 passes through a non-linear gain control circuit 68an then to the multiplexer 70, the output of which passes to the valvedriver of the anti-skid valve.

Also included as part and parcel of the anti-skid FPGA simulation 50 isa skid detector 74, receiving the filtered wheel speed signal from thenotch filter 56. As will be appreciated by those skilled in the art, theskid detector 74 detects instantaneous large changes in wheel speed,identifies the same, and passes such signals to the multiplexer 70 forand instantaneous release of brake pressure, if necessary. The output ofthe skid detector 74 is also passed to the modulator 72 to charge themodulator which, as is known to those skilled in the art, is anintegrator establishing an output signal, applied to the anti-skidvalve, corresponding to the average skid activity of the associatedwheel. In this regard, the output of the skid detector 74 is passedthrough staged gain control circuits 76 to the modulator 72. A timer 78is interposed to delay any transfer of signals which might be attributedto strut reaction to braking activity from the first differentiator tothe modulator 72 immediately after the skid detector turns off. In otherwords, the timer 78 allows a delay in signal transfer sufficient toallow strut reactions to damp out following skid recovery.

Also provided as part and parcel of the anti-skid FPGA simulation 58 isa high pass filter 80, receiving the deceleration output signal of thehigh pass filter 60. This filter 80 serves to pass all signals exceptthose that have a relatively constant value. The output of the filter 80is passed from a second order low pass filter 80 a to a rectifier 82such that the output thereof is a rectified signal (absolute value)corresponding to changes in wheel speed deceleration. The pulses of therectified signal are passed to a peak detector 84 in which sequentialdata pairs are compared, and the maximum held. The output of the peakdetector 84 is passed to the summer 86 and thence to the modulator 72.Thus, it will be appreciated that the anti-skid circuit 58 receives amultitude of signals corresponding to skidding activity of theassociated aircraft wheel. An on/off signal is received from the skiddetector 74, an integrated or average signal is received from themodulator 72 and an anticipatory or derivative signal is received fromthe differentiators 60, 62.

Consistent with the concept of the instant invention, the anti-skidcontrol algorithm 58 of FIG. 2 is reduced to field programmable gatearray implementation by employment of appropriate transfer functionswhich should be perceived by those skilled in the art of FPGAtechnology. With reference to FIG. 3, it can be seen that the low passfilter 54 may be defined by FPGA simulation in the manner depicted inFIG. 3. The low pass filter 54 includes a multiplier or amplifier 90interconnected to an adding circuit 92, the output of which is fed backthrough an amplifier 94 to a subtracting circuit 96, the output of whichpasses through a sample period delay circuit 98 and is then fed to thesummer or adding circuit 92. Those skilled in the art will appreciatethat FIG. 3 presents the block set for the low pass filter 54 which,when appropriately scaled in accordance with the desired transferfunction, will allow the FPGA 12 to be properly routed to perform thelow pass filter function.

The block set 70 for the second order low pass filter 80 a of FIG. 2 isshown in FIG. 4. The input passes to a multiplier or amplifier 100 whichpasses to an adder or summing circuit 102, the output of which passes toa subtracting circuit 104 which includes a feedback circuit of sampledelays 106, 108 and multiplier or amplifier 110. A second feedbackcircuit interconnects the output of the substracter 104 and the adder102 through the sample delay 106 and amplifier or multiplier 112. Again,those skilled in the art will appreciate that implementation ofappropriate scaling and transfer functions will allow the FPGA 12 to beproperly routed to perform the functions set forth in FIG. 4 to achievethe desired second order low pass filter configuration.

Each of the various functions of the anti-skid simulation of FIG. 2 maybe reduced to a block set with appropriate scaling and transferfunctions to allow for the appropriate routing of the FPGA 12 to performthe associated functions. Accordingly, the entirety of the anti-skidfunction of FIG. 2 can be incorporated into the structure of the FPGA12. In like manner, other subsystems of the brake control system 10 canbe similarly reduced to an FPGA implementation, such as nose wheelsteering, automatic braking, brake temperature monitoring, and the like.

Thus it can be seen that the objects of the invention have beensatisfied by the structure presented and described above. The algorithmsof the brake control system can be reduced to the desired scaling andtransfer functions necessary to implement an FPGA routing to accomplishthe necessary function, thereby alleviating the need for discretecomponents or electronic chips given to obsolescence.

1. A brake control system for a wheeled vehicle, comprising: a fieldprogrammable gate array configured to perform an algorithm of brakecontrol subsystems taken from the group comprising anti-skid control,nosewheel steering, brake temperature monitoring, and built-in tests; awheel speed interface interposed between wheel speed transducers of saidwheeled vehicle and said field programmable gate array for presentingsignals to said field programmable array corresponding to instantaneouswheel speed; and a brake temperature interface interposed between brakesof said vehicle and said field programmable gate array and providingsignals corresponding to brake temperature.
 2. The brake control systemaccording to claim 1, further comprising a comparator interposed betweenanti-skid brake valves and said field programmable gate array, saidcomparator providing signals to said field programmable gate arraycorresponding to anti-skid brake valve current and voltage.
 3. The brakecontrol system according to claim 2, wherein said field programmablegate array provides brake control signals to said anti-skid valves. 4.The brake control system according to claim 2, wherein said fieldprogrammable gate array provides brake control signals to said anti-skidvalves.
 5. The brake control system according to claim 1, wherein saidanti-skid control subsystem comprises: a frequency to digital converterreceiving wheel speed signals and passing said wheel speed signalsthrough low pass and notch filters, generating filtered wheel speedsignals; first and second interconnected differentiators receiving saidfiltered wheel speed signals, generating first and second derivatives ofwheel speed.
 6. The brake control system according to claim 4, whereinsaid anti-skid control system further comprises a limiter connected tosaid first and second interconnected differentiators for limiting thesignal corresponding to the second derivative of wheel speed.
 7. Thebrake control system according to claim 5, wherein said anti-skidcontrol system further comprises a modulator operatively connected to ananti-skid valve driver and providing thereto an instantaneous averagewheel speed signal.
 8. The brake control system according to claim 6,wherein said anti-skid control system further comprises a skid detectorpassing output signals corresponding to instantaneous large changes inwheel speed to said anti-skid brake control valve driver and saidmodulator.